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Instead of simply using one carry-save adder over and over to add one partial product after another, or to have a single line of carry-save adders if it is desired to do successive steps from different multiplications at once in a pipelined fashion, if maximum speed is desired and the cost of hardware and the number of transistors used is no object, one could, as shown above, use several carry-save adders in parallel to produce two results from three partial products, and then repeat the process in successive layers until there are only two numbers left to add in a fast carry-propagate adder.

One form of this kind of circuit, arranged according to a particular procedure intended to optimize its layout, is known as the Wallace Tree adder; this was first described in , and an improvement, the Dadda Tree adder, was described in Six partial products were handled by this unit, which were generated from thirteen bits of the multiplier.

To avoid having to calculate three times the multiplicand, instead of using two bits of the multiplier for each partial product, sets of three bits that overlapped by one bit were used.

To continue the overlap, the groups of thirteen bits also overlapped by one, so that each iteration took care of twelve bits of the multiplier. The code used was: But the groups of three bits, being overlapped by one bit, differ in value by a factor of four, not eight.

There is a problem working this scheme in the way that seems correct, though; is zero, is one, is two, but is three. But there is a reason why 8 is correct: Anyways, this scheme is the one described later on this page as Booth encoding. However, precomputing those multiples would have been slower than using Booth encoding. The description of that unit in U.

Incidentally, there is a misprint in the patent: Patent 2,, rather than the number appearing. On the other hand, the Intel Pentium 4 used a larger Wallace Tree, with 25 inputs, which, after Booth encoding, was large enough that floating-point numbers of up to 64 bits in length in IEEE format, and thus with an effective mantissa of 53 bits, including the hidden first bit could be multiplied without a second trip through the unit, and thus such multiplies could be pipelined. Incidentally, note that this means that a more advanced form of Booth encoding was used in the Pentium 4 than the one used in the Model 91, which only cut the number of multiplier terms in half, and which, thus, would only have allowed up to 50 bits, not 53 bits, to be reduced to 25 terms for addition.

An alternative method of speeding up multiplications by using a scheme of addition that avoids having to possibly propagate carries across the entire width of a number is known as signed digit multiplication. For example, a signed radix-4 number can be converted to a form consisting of the signed digits -3, -2, -1, 0, 1, 2, and 3, still with 4 as the radix.

The sum of two such numbers will be in the range of -6 to 6. If that sum is generated in the form of a carry digit and a sum digit in the form shown in the table below: Thus, two stages of circuitry are sufficient to perform a signed-digit addition without regard for the size of the numbers involved. This is a redundant representation of numbers, so at first glance this does not seem to be that much different from Wallace Tree addition.

However, it does have the important advantage that instead of summing three numbers to two, it sums two numbers to one. While this takes two stages, so it doesn't mean this is faster than Wallace Tree addition, it can provide for a tidier layout of circuitry on a chip, and this was cited as its major benefit.

The half adder, although it takes two inputs and provides two outputs, has been used to improve the Wallace Tree adder slightly. One way this has been done is: Although this produces two outputs, one of those outputs will consist of carries, and will therefore be shifted one place to the left.

If the number of terms to be added in the next stage is still not an even multiple of three, then, at least at the beginning and end of the part added in the half adders, the number of left-over bits will be reduced by one.

The Dadda Tree multiplier uses this, and in other ways takes the fact that the carry bits are moved from one digit to another into account so that each layer of the tree for each digit will, as far as possible, work efficiently by acting on a number of input bits that is a multiple of three.

This is basically achieved by delaying putting groups of three input bits into a carry-save adder until later stages where this is possible without increasing the number of stages.

More recently, in U. Patent 6,,, assigned to the Digital Equipment Corporation, the fact that half the input bits are moved to the left as carry bits was noted explicitly as a way to replace the larger tree generating the middle of the final product by multiple trees of more equal size starting from the middle and proceeding to the left. As noted above, one could trim away a considerable portion of the addition tree by using two digits of the multiplier at a time to create one partial product.

But doing this in the naive way described above requires calculating three times the multiplicand, which requires carry propagation. Another idea that suggests itself is to note that either less than half of the bits in a multiplier are 1, or less than half of the bits in a multiplier are zero, so that in the former case, one could include only the nonzero partial products, and in the latter case, one would multiply by the one's complement of the multiplier and then make a correction.

But this would require an elaborate arrangement for routing the partial products that would more than consume any benefits. Fortunately, there is a method of achieving the same result without having to wait for carries, known as Booth encoding. The original paper describing this was published in The goal is to make it possible for each pair of bits in the multiplier to introduce only one partial product that needs to be added.

Normally, each pair of bits calls for 0, 1, 2, or 3 times the multiplicand, and the last possibility requires carry propagation to calculate. Knowing that -1 is represented by a string of ones in two's complement arithmetic, the troublesome number 3 presents itself to us as being equal to 4 minus 1. Four times the multiplicand can be instantly generated by a shift. The two's complement of the multiplicand would require carry propagation to produce, but just inverting all the bits of the multiplicand gives us one less than its additive inverse.

It is possible to combine bits representing these errors, since each time this happened, it would be in a different digit, in a single term that could be entered into the addition tree like a partial product. Or it could be placed within another term of the product that lies entirely to the left of its location.

But that, alone, doesn't eliminate carry propagation. As it happens, though, we have one other possible value that can be produced without carry propagation from the multiplicand that is useful. We can also produce -2 times the multiplicand by both shifting it and inverting it; this time, the result will also be too small by one, and that, too, can be accounted for in the error term.

Using the fact that -2 is also available to us in our representation of pairs of bits, we can modify the pairs of digits in the multiplier like this: A second step is not really needed, since one just has to peek at the first digit of the following pair of bits to see if a carry out would be coming; thus, Booth coding is often simply presented in the manner in which it would be most efficient when implemented, as a coding that goes directly from three input bits to a signed base-4 digit: This serves as a reminder that the last bit encoded is to the right of the place value of the result of the code, and also that the rightmost pair of bits is encoded on the basis of a 0 lying to their right.

Of course, the final carry out, not apparent in this form of the table, should not be forgotten; but it can also be found by coding an additional leading two zero bits appended to the multiplier.

And the digits of the multiplier as converted can be used to determine the value of the error term. In addition to the error term, it is also necessary to remember that the partial products can be negative, and so their signs will need to be extended; this can be done by means of extending the various carry-save adders in the Wallace tree only one additional bit to the left with proper organization.

If the multiples of the multiplicand are generated in advance, and the multiplier is long enough, then one can retire four bits of the multiplier and, using a pre-generated multiple, following the principle used in the NORC, do so with only a single carry-save addition. If the multiples are not generated in advance, or when a full-width Wallace Tree is used, it would seem that multi-bit Booth encoding could not provide a gain in speed, because an addition requiring carries would take as long as several stages of carry-save addition.

If one is retiring the bits of the multiplier serially, to save hardware, rather than using a full Wallace Tree, in which all of the multiplier is retired at once, and the partial products are then merged into half as many terms at each step, one could retire the last few bits of the multiplier at a slower rate while waiting for the larger multiples of the multiplicand to become available.

The Alpha multiplier unit used this technique, using Booth encoding of bit pairs in the multiplier until a conventional adder produced the value of three times the multiplicand for use in later stages allowing the use of three-bit Booth encoding of the multiplier thereafter. Some early large and fast computers, such as the Elliot and the Whirlwind, before either the carry-save adder or Booth recoding were invented, speeded up multiplication by using a tree of ordinary adders. A multiplication unit of this type was called a whiffletree multiplier, after a type of harness for two draft animals that ensures that both contribute useful work even if they aren't pulling equally hard.

Division Division is the most difficult of the basic arithmetic operations. For a simple computer that uses a single adder circuit for its arithmetic operations, a variant of the conventional long division method used manually, called nonrestoring division provides greater simplicity and speed.

This method proceeds as follows, assuming without loss of generality which means we can fix things by complementing the operands and remembering what we've done, if it isn't so that both operands are positive: If the divisor is less than the dividend, then the quotient is zero, the remainder is the dividend, and one is finished.

Otherwise, shift the divisor as many places left as is necessary for its first one bit to be in the same position as the first one bit in the dividend.

Also, shift the number one the same number of places left; the result is called the quotient term. The quotient value starts at zero. Then, do the following until the divisor is shifted right back to its original position: If the current value in the dividend register is positive, and it has a one bit corresponding to the starting one bit of the value in the divisor register initially, the divisor as shifted left , subtract the divisor register contents from the dividend register, and add the quotient term to the quotient register.

If the current value in the dividend register is negative, and it has a zero bit corresponding to the starting one bit of the value in the divisor register, add the divisor register contents to the dividend reigster, and subtract the quotient term from the quotient register. Shift the divisor register and the quotient term one place to the right, then repeat until finished when the quotient term becomes zero at this step, do not repeat.

If, after the final step, the contents of the dividend register are negative, add the original divisor to the dividend register and subtract one from the quotient register. The dividend register will contain the remainder, and the quotient register the quotient. An example of this is shown below: Divide by Speeding up division further is also possible. One approach would be to begin with the divisor, from which 8, 4, and 2 times the divisor can be immediately derived, and then with one layer of addition stages, derive 3 and hence 6 and 12 times the divisor, 5 and hence 10 times the divisor, and 9 times the divisor, and then with a second layer of addition stages, derive the remaining multiples from 1 to 15 of the divisor.

Then an assembly of adders working in parallel to determine the largest multiple that could be subtracted from the dividend or the remaining part of it without causing it to go negative could generate four bits of the quotient in the time a conventional division algorithm could generate one.

The decimal version of this technique was used in the NORC computer, a vacuum tube computer designed for very high-speed calculation. Another method of division is known as SRT division.

In its original form, it was a development of nonrestoring division. Instead of choosing, at each bit position, to add or subtract the divisor, the option of doing nothing, and skipping quickly over several bits in the partial remainder, is also included. Starting from the same example as given above for nonrestoring division: When the partial remainder is negative, we align the divisor so that its first 1 bit is under the first zero bit of the partial remainder,and add; we subtract a similarly shifted 1 from the quotient.

In the example, an immediate stop is shown when the right answer was achieved; normally, two additional steps would take place; first, a subtraction of the divisor, and then, since the result is negative, an addition in the same digit position; this is the same second chance without shifting as is used to terminate nonrestoring division. The property of shifting at once over multiple zeroes is no longer present in the high-radix forms of SRT division.

Thus, in radix 4 SRT division, one might, at each step, either do nothing, add or subtract the divisor at its current shifted position, or add or subtract twice the divisor at its current shifted position.

Instead of a simple rule of adding to a zero, and subtracting from a 1, a table of the first few bits of both the partial remainder and the divisor is needed to determine the appropriate action at each step.

Newton-Raphson Dvision To achieve time proportional to the logarithm of the length of the numbers involved, a method is required that attempts to refine an approximation of the reciprocal of the divisor. The recurrence relation can be made more understandable by splitting it into two parts. Thus, the second multiplication can be part of the equation: We will see how this can be used below.

Goldschmidt Division Another method of performing division, which also converged quadratically, and required two multiplications for each iteration, was Goldschmidt division.

It was described in U. This method had one disadvantage over Newton-Raphson division, in that the earlier multiplications could not be done at less than full precision. But it had the larger advantage that the two multiplications in each step were independent of one another, and so they could be done in parallel, or on successive cycles in a single pipelined multiplication unit.

Its basis is the binomial theorem: The reciprocal of 9 is 0. Quadratic convergence can be obtained by steps like this: Although each step in the Goldschmidt algorithm has to be done at the full precision of the final result, another option would be to use the Goldschmidt algorithm at slightly more than half precision for all the steps except the last one, and then use the Newton-Raphson algorithm for the final step to increase the precision to that desired.

If the time saved by doing all the previous steps at half precision exceeds the time taken by an additional multiplication, that could be worthwhile. As well, one source I've recently read noted that this is a useful choice for quite another reason: Therefore, if good accuracy, even if not the perfect accuracy demanded by the IEEE standard, is a requirement, and performing the Goldschmidt algorithm to somewhat greater precision than the target precision is not an option, as it is not desired to face an additional hardware requirement for this specialized purpose, doing the last round with the Newton-Raphson algorithm allows roundoff errors to be overcome.

One obstacle to the use of existing hardware is that since double-precision numbers tend to take exactly twice the storage of single-precision numbers, but their exponent fields are not twice as long even where, as in the IEEE standard, they aren't exactly the same size , doing the Goldschmidt algorithm in single precision and then Newton-Raphson in double precision for just one round won't quite work; in that case, one simple option would be to do Newton-Raphson for two rounds, at the cost of an extra multiply time.

Of course, the more usual case is where there is only one set of floating-point hardware, and so the previous Goldschmidt rounds were done to full precision; in which case, of course, one final Newton-Raphson round would suffice. Corrected Rounding One difficulty with the use of both of these iterative methods for division is that they do not naturally lend themselves to producing the most accurate result in every case, as required by the IEEE standard.

The obvious way of dealing with this is as follows: Because the accuracy of that approximation doubles with each iteration, there will be some excess precision available at the final iteration. If the part of that result that needs to be rounded off to fit the quotient into the desired format is close enough to. Multiply it by b, the divisor. If the result is greater than a, then.

If the result is less than a,. Because allowing a division to take a variable amount of time could interfere with pipelining in some computer designs, work has been done on finding improved algorithms for IEEE compliant Goldschmidt division. I have seen a claim that a patent from , U. Incidentally, that patent also referenced another patent, which dealt with signed digit multiplication, that technique also having been used on that chip.

However, the process described in that patent still requires multiplying the final quotient by the divisor in the final step to determine the direction of rounding. However, that final step of multiplication could be performed using only the last few bits of the numbers involved, and so my initial impression that the existing state of the art, as indicated by the patents I had reviewed, required either two sets of division hardware working in parallel, or an extra full-width multiplication adding to the latency of the operation, was mistaken, and instead IEEE compliant rounding can be achieved at reasonable cost in both hardware and time for division.

Several engineers working at Matsushita, Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Masashi Urano, Hisakazu Edamatsu, and Shigero Kuninobu, developed a method of adapting iterative division to produce accurate results with a very limited latency overhead which was published in a paper.

Markstein, and which is the subject of U. Intel's own improvement to this is given in U. Harrison being the inventor. Other research and patents from Matsushita involving several of these same engineers related to improving another characteristic of division algorithms.

In order to perform an iterative division, how often is it really necessary to perform the final step in multiplication, creating an explicit numerical result at the cost of carry propagation? Perhaps it is not necessary at all, except once at the very end. A table-driven method of division for arguments of limited width, described in a paper by Hung, Fahmy, Mencer, and Flynn, can also be used to obtain an excellent initial approximation to the reciprocal in the time required for two multiplications; conventional techniques can then double the precision of the approximation in each additional multiplication time used.

To divide A by B: B will be normalized before starting, so that its value is between 1 and 2. In the second multiplication time, multiply, in parallel, both the modified A and the modified B by the product involving the remaining bits of B. The following is our sorted array and let us assume that we need to search the location of value 31 using binary search.

So, 4 is the mid of the array. Now we compare the value stored at location 4, with the value being searched, i. We find that the value at location 4 is 27, which is not a match. As the value is greater than 27 and we have a sorted array, so we also know that the target value must be in the upper portion of the array. We compare the value stored at location 7 with our target value The value stored at location 7 is not a match, rather it is more than what we are looking for.

So, the value must be in the lower part from this location. Hence, we calculate the mid again. This time it is 5. We compare the value stored at location 5 with our target value. We find that it is a match.

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